1. Field of the Invention
The present invention relates to clock switching circuitry applicable to, e.g., a bit synchronizing circuit for a high-speed transmission interface for receiving input data timed with one clock and developing the input data in synchronized with another clock different in phase from the one clock.
2. Description of the Background Art
Clock switching circuitry is disclosed in, e.g., Japanese patent laid-open publication No. 268201/1993 (Document 1 hereinafter) and Japanese Patent No. 3119793. The circuitry taught in Document 1 includes a plurality of memories. When writing the memories, input data are written into the memories in timed with a write clock while sequentially switching the memories frame by frame of the input data. On the other hand, when reading the memories a read clock is supplied to read out the data from the memories while sequentially switching the memories frame by frame. As a result, the data are transferred from the write clock to the read clock.
The circuitry of Document 1 includes a phase monitor and a phase controller. The phase monitor detects a conflict occurring between the write phase and the read phase in the same memory. When the phase monitor detects a conflict, the phase controller varies the read phase and thereby sets up a preselected phase difference between the write phase and the read phase. It is to be noted that a conflict refers to, e.g., an occurrence that data writing and data reading of the same storage location of an address occur at the same time. A conflict causes data, while being written into the storage location, to be read out halfway, resulting in incorrect data. It is therefore necessary to surely detect a conflict and prevent it from repeating. With the above configuration, the circuitry of Document 1 can switch the clock without resorting to a digital-to-analog converter and an analog-to-digital converter heretofore essential for clock switching.
However, the circuitry of Document 1 has some problems left unsolved, as will be described hereinafter. The write clock dominating the write phase in an address space and the read clock dominating the read phase out of the address space are not synchronous to each other, i.e., not always coincident in phase with each other. Moreover, to detect a conflict, the phase monitor compares the phase of a write window pulse derived from the asynchronous write phase with the phase of a read pulse, i.e., produces an AND of the two pulses. This kind of scheme fails to surely detect a conflict itself.
For example, assume that the phase monitor determines that a conflict has occurred when the high level of the write window pulse and that of the read pulse overlap each other. Then, the duration of the overlap is likely to be extremely short, e.g., shorter than the duration of a single clock pulse because the two pulses are not synchronous to each other. Generally, the above duration may even be shorter than a period of time necessary for a flip-flop or a latch to be set up and hold data. In such a case, correctness of data held in the flip-flop or the latch cannot be guaranteed, resulting in low reliability.
On the other hand, a CAD (Computer Aided Design) tool may often be used to design the clock switching circuitry in the same manner as to design electronic circuits in general. In this respect, the write window pulse and read pulse not synchronous to each other prevent a simple software macro-function, which can work sufficiently only by specifying functions of a clock switching circuitry, from being used with the CAD tool. Therefore, to design a clock switching circuit, use must be made of a hardware macro-function for specifying even the layout of the individual circuit devices in detail. It makes design work difficult to perform.
It is an object of the present invention to provide clock switching circuitry capable of detecting a conflict with high reliability and facilitating design work using a CAD tool.
Clock switching circuitry of the present invention includes a memory having a plurality of storage locations of a particular address each. The memory allows data to be written into and read out from each storage location at the same time. A write pointer causes a write address addressing a storage location to vary in synchronism with a write clock. A read pointer causes a read address addressing a storage location to vary in synchronism with a read clock. A synchronizer selectively executes first synchronization for synchronizing the phase of the write address with the read clock to generate a synchronized write address or second synchronization for synchronizing the phase of the read address with the write clock to generate a synchronized read address. A conflict detector outputs an alarm signal when determining that a phase difference between the write address and the synchronized read address is smaller than a preselected reference value or that a phase difference between the read address and the synchronized write address is smaller than the preselected reference value. A conflict avoiding circuit executes, in response to the alarm signal, a conflict avoiding operation that causes the write address and read address to differ form each other by at least the reference value.